AN EXPERIMENT ON UART ENABLED BUILT-IN-SELF-TEST USING VERILOG ABSTRACT

AN EXPERIMENT ON UART ENABLED BUILT-IN-SELF-TEST USING VERILOG
ABSTRACT: Asynchronous serial communication is generally implemented by the asynchronous transmitter (UART) of the universal receiver, normally used to alternate information of short and low speed between the processor and peripherals. The UART allows the connection of serial full-duplex messages and is used in data communication and in the operating system. It is necessary to execute the UART function in only one or a few chips. In addition, design systems without full testability are open to the increasing possibility of product failures and loss of market opportunities. It is also necessary to ensure that the data transfer is error-proof. This project focuses on the introduction of the integrated self-test (BIST) and the status register of the UART. The basic idea is to reduce as much as possible the alternation between the test models. In this approach, the patterns to change a single input generated by a counter and a gray code generator are Exclusive-ORed with the seed generated by the linear displacement recorder with linear feedback LP-LFSR. The 8-bit UART with state register and BIST module is encoded in Verilog HDL and synthesized and simulated with Xilinx XST and ISim version 14.4 and implemented in FPGA.

Keywords: – BIST Architecture, UART Tx,
UART Rx, LFSR, VLSI testing.

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INTRODUCTION:
The electronics industry has achieved phenomenal growth in the last two years
For decades, mainly due to the rapid progress of integration technologies, the design of large-scale systems, in short, due to the arrival of the VLSI. The number of applications of integrated circuits in high performance computing, telecommunications and consumer electronics continued to increase, and at a very fast pace. Generally, the required computing power (or, in other words, intelligence) of these applications is the driving force for the rapid development of that field. It provides an overview of key trends in information technology in the coming decades. The latest technologies (such as low-bit-rate videos and cellular communication) already offer end users some computing power and portability. This trend should continue, with very important implications for VLSI and system design. One of the key features of information services is the growing need for very high processing power and bandwidth (for example, video processing in real time). Another important feature is that information services are increasingly customized (as opposed to collective services such as broadcasting), which means that devices need to be smarter to meet individual needs at the same time they must be portable to allow more flexibility/mobility.
Integration on a very large scale (VLSI) is the process of creating integrated circuits, combining thousands of circuits based on transistors on a single chip. The VLSI began in the 70s, when complex semiconductor and communication technologies were developed. The microprocessor is a VLSI device. The term is no longer as common as before, because chips have increased in complexity in the hundreds of millions of transistors.

BIST ARCHITECTURE
The BIST architecture consists of visualizing the Standard Generator (TPG), the circuit to be tested (CUT), the way of examining the results (TRA) and a way to analyze these results (BCU) and also LFSR to simplify. compress and manipulate. The CUT could be designed as an architecture of a memory device to test errors. The error address can be detected and compared with the comparator for the analysis of all relevant circuits.

Figure 1: Block diagram of BIST architecture
The LFSR generates the feedback values of each flip-flop for new CUT architecture. The level of recognition can be difficult to identify the error and may require a long process. The process can be used for all authorized and unauthorized data. The BIST driver can be easily controlled as device details for the new architecture for more details. The analysis of the test response can be considered for the UART transmission and the form of the reception data of each bit. The results of the test can detect the error address and then consume all the details as a database and identify the error address and show the details. This could be a waveform process of the simulation level.

UART ARCHITECTURE
A universal asynchronous receiver / transmitter, abbreviated as UART, is a hardware device that converts data between characters (usually bytes) in a computer and an asynchronous serial communication format that encapsulates these characters between the initial and final bits.

The UART architecture contains the transmitter and the receiver. This can contain and load buffer data for all read and write operations. The data is transmitted via this serial communication to obtain the correct information on the outputs.

Figure 2: Block diagram of UART Architecture
UART COMMUNICATION
In UART communication, two UARTs communicate directly with each other. The UART transmission converts parallel data from a control device, such as a serial CPU, sends them in series to the receiving UART, which then converts the serial data into data parallel to the receiving device. Only two cables are needed to send data between two UARTs. The data flow from the Tx pin of the sending ART to the Rx pin of the receiving UART

Figure 3: UART communiatiion
The universal asynchronous receiver / transmitter (UART) receives data bytes and sends the individual bits in sequence. At the destination, a second UART groups the bits into complete bytes. Each UART contains a shift register, the basic method for converting between serial and parallel modules. Serial transfer of digital information (bits) via a single cable or other means is less expensive than parallel transmission via multiple cables.

IV. SIMULATION RESULTS
The simulation of the UART BIST architecture can be done through the Xilinx ISE using the VERLOG HDL. Checking the data address bits can also be done using this simulation and the waveform can be verified using MODELSIM.

Figure 4: Architecture of UART
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Figure 5: Waveform of UART architecture

Figure5: Architecture of BIST

Figure 7: Waveform of BIST architecture

Figure 8: Architecture of LFSR

V.CONCLUSION
This document presents the UART-based BIST architecture using VERLOG HDL. Most researchers have been used to implement this VERILOG test algorithm for stable, compact and reliable transmission. The structural details have been recognized and can be integrated into the chip could be easier. The UART transmission could be used relatively on all devices for reliable transmission of data from the structure in which it could be converted and tested as a generation of bit files. This design function can be adopted as technical conservation data for communication. The BIST controller as a device is used as efficient bit generation for the chip implementation.

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